; ; Copyright (c) 1995-1999 by Mentec, Inc., U.S.A. ; All rights reserved ; ; ; This software is furnished under a license and may ; be used and copied only in accordance with the ; terms of such license and with the inclusion of the ; above copyright notice. This software or any other ; copies thereof may not be provided or otherwise ; made available to any other person. No title to ; or ownership of the software is hereby transferred. ; ; The information in this software is subject to ; change without notice and should not be construed ; as a commitment by Digital Equipment Corporation. ; ; Digital assumes no responsibility for the use or ; reliability of its software on equipment that is ; not supplied by Digital. ; ; ; Previously Modified by: ; J. Kauffman ; Eric Postpischil ; ; Re-mastered for RSX-11M-PLUS V4.4 by: ; ; L. B. McCulley 29-Dec-91 4.00 ; LBM409 -- Major changes for bug fixes addressing ; read/write interactions and general cleanup ; ; D. Carroll 10-October-1992 ; DC143 -- Define bugcheck definitions for cache ; ; D. Carroll 1-Nov-1992 4.03 ; DC151 -- other cleanup functions/optimizations ; ; D. Carroll 21-Nov-1992 4.04 ; DC156 -- add pseudo-write-behind support by conditional ; ; D. Carroll 04-Dec-1992 4.05 ; DC157 -- Impliment a cache hash table for SEARCH ; ; Modified for RSX-11M-PLUS V4.6 by: ; ; D. Carroll 08-Jan-1996 05.00 ; DC430 - Include support for 32-bit LBNs ; ; ; ; Prefix file for disk data caching ; ; Note that the data mapping is different for I/D and ; non-I/D systems. In order to offer maximal data ; space for the [larger] I/D systems, kernel data space ; will be used to map the cache partition header. This ; provides up to 16KB of cache data structures which ; should be more than adequate. However, special handling ; is provided for local data. ; For non-ID systems, only APR6 is used to map the partition. ; This sets a limit of 8KB on the data structures. Under ; normal use, this would place a virtual limit on the cache ; date buffer to about 512KB, since there would ; be data structure allocation shortages on partitions ; in excess of 512KB. ; ; NOTES ON ADDRESSING RESTRICTIONS: ; ; Note that the cache code itself cannot rely on local data ; within the cacher module itself. On non-I/D systems, only ; APR6 can be used to reference the partition's pool area. ; This limits the pool size to 4KW. ; On I/D systems, D-space is used to reference 8KW in both ; APR5 and APR6. ; ; The UCB extension (UCBX) is mapped in APR6, as a ; convention. It is usually mapped only in the dispatching ; code, and may be dynamically (temporarily) mapped to access ; the cells used to maintain the device-specific listheads. ; ; The cache statistics buffer is also only mapped in APR6. ; It is also dynamically (temporarily) mapped by the macro ; USTAT$ (Update STATistics), in the various pieces of code. ; ; The actual cache buffers themselves are never directly mapped ; during operation, although the executive subroutine $BLXIO ; will map them to transfer data. ; ; CHEWBH = 0 ; Define to enable write-behind support CHEDFR = 0 CHESTS = 0 ;Define to enable cache statistics ; ; Macro calls ; .MCALL CHEDF$ ;Cache definitions .MCALL FILIO$ ;File oriented I/O definitions .MCALL PKTDF$ ;Packet definitions .MCALL QIOSY$ ;QI/O error and code definitions .MCALL UCBDF$ ;UCB[X] definitions .MCALL BGCK$A,BCKDF$ ; Define bugcheck macro, and definitions BCKDF$ ; Define bugcheck definitions CHEDF$ FILIO$ PKTDF$ QIOSY$ UCBDF$ .IF DF CHEWBH WS.WBH = 100 ; internal write behind flag .ENDC ;DF,CHEWBH ; ; Macro definitions ; ; ; MP.UCBX - Map UCBX in KISAR6 (replaces call to single instruction subr ; .MACRO MP.UCBX ; Assumes UBC ptr in R5 MOV U.UCBX(R5),KISAR6 ; Map UCB's UCBX in APR 6 .ENDM MP.UCBX ; ; MP.PAR - Map cache partition in KISAR6 or KISAR5 & KISAR6 (if kernel I/D) ; .MACRO MP.PAR ; Assumes UCB ptr in R5 MP.UCBX ; Map UCBX to get cache address MP$PAR .ENDM MP.PAR ; ; MP$PAR - Map cache partition in KISAR6 or KISAR5/6 if I/D ; .MACRO MP$PAR MOV R0,-(SP) ; Save a register MOV APR6.BASE+X.CPCB,R0 ; Get address of cache PCB MOV P.REL(R0),KISAR6 ; Map partition in APR6 MOV (SP)+,R0 ; Restore register .IFDF K$$DAS ; Kernel I/D executive? MOV KISAR6,KISAR5 ; I/D systems allow 8KW ADD #200,KISAR6 ; Always map accordingly .ENDC ; K$$DAS .ENDM ; MP$PAR ; ; FATAL$ macro, used to declare cache inconsistencies ; .MACRO FATAL$ ERR BGCK$A BF.CHE,'ERR', .ENDM ;FATAL$ ; ; USTAT$ - Update Statistics Buffer ; .MACRO USTAT$ OFFSET,BASE .IF DF CHESTS ; Cache statistics enabled? .IF NB MOV BASE,-(SP) ; load base address MOV #, (R1) ; load the offset, and flag base .IFF ;NB, MOV #OFFSET, (R1) ; assume R1 => i/o pkt .IFTF ;NB, CALL $USTAT ; use I.LNK as param passing link .IFT ;NB, TST (SP)+ ; clean stack .ENDC ;NB, .ENDC ; .IFDF CHESTS .ENDM USTAT$ ; ; CRP (Cache Request Packet) definitions ; CRP stores I/O request context in cache internal pool ; .SAVE .ASECT .=0 R.URP: .BLKW 1 ; Pointer to associated User Request Packet R.STAT: .BLKW 1 ; Status block context (base offset for USTAT) R.LBNH: .BLKW 2 ; Disk extent high LBN (LSP, MSP) ;DC430 R.LBNL: .BLKW 2 ; Disk extent low LBN (LSP) ;DC430 R.FCN: .BLKB 1 ; I.FCN modifiers from user I/O pkt ;**-3 R.EFN: .BLKB 1 ; I.EFN virtual op flag from user pkt R.IOSB2: .BLKW 1 ; I.IOSB+2 from user pkt .BLKW 1 ; I.IOSB+4 from user pkt R.P1.1: .BLKW 1 ; I.PRM+P1 from user pkt R.P1.2: .BLKW 1 ; I.PRM+P1 word 2 from user pkt R.P2: .BLKW 1 ; I.PRM+P2 from user pkt R.P3: .BLKW 1 ; I.PRM+P3 from user pkt R.P4: .BLKW 1 ; I.PRM+P4 from user pkt R.P5: .BLKW 1 ; I.PRM+P5 from user pkt R.AADA: .BLKW 2 ; I.AADA from user pkt ; I.AADA+2 from user pkt R.LGTH=. .RESTORE ; ; Offset definitions in I.PRM ; P1 = 0 ;Parameter 1 (I.PRM+0) P1.1 = 0 ; P1.2 = 2 ; P2 = 4 ;Parameter 2 (I.PRM+4) P3 = 6 ;Parameter 3 (I.PRM+6) P4 = 10 ;Parameter 4 (I.PRM+10) P5 = 12 ;Parameter 5 (I.PRM+12) P6 = 14 ;Parameter 6 (I.PRM+14) P6.1 = 14 ;[UQ.UMD] P6.2 = 16 ;[UQ.UMD] ; ; Cache specific offsets within an IOP ; I.CRP = I.AADA ; CRP address I.ACED = I.AADA+2 ; Address of attached CED ; ; Symbols used internally as "base values" for APR relocation ; APR5.BASE = 120000 ;Base address for APR5 reference APR6.BASE = 140000 ;Base address for APR6 reference .IF DF K$$DAS ;Kernel I/D space supported APRD.BASE = APR5.BASE ;Data begins in APR5 .IFF ;K$$DAS APRD.BASE = APR6.BASE ;Non-I/D systems begin in APR6 .ENDC ; ; Macro status bits ; ; CHEBYP: All modifiers in the function code to indicate that ; the operation is to be cache bypassed. ; ; EXBUSY: All bits which mark the extent as "busy" or locked ; pending the completion of another process. ; ; CHEBYP = ;<1!2!4=7> If set, request is "bypass" EXBUSY = ;<> If set, extent in use or locked ; ; Definitions for large extent transfers. ; MAXTR = 17700 ; size of largest permissible transfer, in bytes MAXTRB = 177 ; size of largest transfer, in 64-byte blocks